PCIe 6.0 Interoperability Demonstrated at FMS 2024: PCI-SIG’s Latest Innovation
PCI-SIG isn’t twiddling its thumbs as PCIe 5.0 starts gaining traction in both data centers and consumer markets. They’re already cooking up the next big thing – PCIe 7.0, which promises 128 GT/s speeds and 512 GBps of bidirectional traffic. Yeah, you read that right, it’s still a ways off, but they’re already working on the specs. At FMS 2024, some vendors were even talking about PCIe 7.0, which is crazy, considering PCIe 6.0 hasn’t even hit the shelves yet. We caught up with PCI-SIG to get the lowdown on their plans and the current state of the PCIe ecosystem.
PCI-SIG has already shared the PCIe 7.0 specs (version 0.5) with its members, and they’re aiming to finalize them by 2025. The goal is to deliver a 128 GT/s data rate with up to 512 GBps of bidirectional traffic using x16 links. Similar to PCIe 6.0, PCIe 7.0 will use PAM4 signaling and maintain backwards compatibility. Power efficiency and silicon die area are also top priorities in the drafting process.
The move to PAM4 signaling does introduce higher bit-error rates compared to NRZ, which means they’ve had to adopt a different error correction scheme in PCIe 6.0. Instead of variable-length packets, PCIe 6.0’s Flow Control Unit (FLIT) encoding operates on fixed-size packets to aid in forward error correction. PCIe 7.0 is following suit.
The integrators list for the PCIe 6.0 compliance program is expected to drop in 2025, with initial testing already underway. At FMS 2024, we saw a demo featuring Cadence’s 3nm test chip for its PCIe 6.0 IP offering, along with Teledyne Lecroy’s PCIe 6.0 analyzer. These timelines align nicely with the specification completion dates and compliance program availability for previous PCIe generations.
We also got an update on the optical workgroup, which is working on developing technology-specific form-factors, including pluggable optical transceivers, on-board optics, co-packaged optics, and optical I/O. The group is enhancing the logical and electrical layers of the PCIe 6.0 specs to accommodate the new optical PCIe standardization, and they’ll do the same for PCIe 7.0 to coincide with its release next year.
The PCI-SIG is also working on cabling initiatives. On the consumer side, we’ve seen significant traction for Thunderbolt and external GPU enclosures. However, even data centers and enterprise systems are moving towards cabling solutions as it becomes clear that disaggregating components like storage from the CPU and GPU is better for thermal design. Plus, maintaining signal integrity over longer distances becomes tricky for on-board signal traces. Cabling internal to the computing systems can help here.
OCuLink emerged as a good candidate and was adopted fairly widely as an internal link in server systems. It’s even made an appearance in mini-PCs from some Chinese manufacturers in its external avatar for the consumer market, although it hasn’t gained much traction. As speeds increase, a widely-adopted standard for external PCIe peripherals (or even connecting components within a system) will become crucial.
